![]() etc.īut if you want to use testbench for simulation, Qaurtus II alone cannot do it, you have to use ModelSim, which again involves "pre-simulation" and "post-simulation". Testbench can use Verilog system functions, such as $display(), $fwrite(). Testbench can describe circuit specifications more flexibly than waveform editor.Ģ. The more recommended way is to learn the ASIC trick: "Write testbench first to simulate each module, then perform post-simulation for each module, and finally burn into the FPGA test. Although this method is feasible, it is only applicable For a small project, if the project gets bigger and bigger, Quartus II just takes a lot of time to do the fitter, and I do Quartus II compilation all day. Use environment: Quartus II 8.1 + ModelSim-Altera 6.3gīecause FPGA can be re-programmed, many developers do not write testbench, directly use Quartus II programmer to burn into the development board to see the results, or use Quartus II's own Waveform Editor for simulation. This article introduces the use of ModelSim for pre-simulation, and Quartus II and ModelSim for post-simulation. ![]() It is more detailed.Ĭan solve the problem "Why does quartusII call modelsim how to compile the library every time" The method inside, I used in writing "Sobel Edge Detection FPGA Application. ![]() (Reposted) How to use ModelSim for pre-simulation and post-simulation? (SOC) (Quartus II) (ModelSim) ![]()
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